1. Field of the Invention
The present invention generally relates to a method (and resultant structure) of forming a semiconductor device, and more particularly to a method (and resultant structure) of forming a dual damascene interconnection.
2. Description of the Related Art
Currently, it is difficult to adequately line contacts for copper filling at contact dimensions below 280 nm, and to line contacts reliably below contact opening sizes of less than 320 nm. This presents a major challenge to dynamic random access memory back-end-of-line (DRAM BEOL) processing that would like to migrate to a copper back-end in the near future.
Additionally, in the conventional methods, there are a large number of types of conducting materials that must be implemented in a BEOL process.
Further, the conventional methods require a separate method for producing DRAM BEOL and a separate method for producing the logic BEOL so that different manufacturing lines are required to produce either DRAM or logic with the same type and number of tools.
Finally, the conventional methods typically attempt to fill substantially both small and large structures with copper, thereby requiring additional and costly processing such as multiple CVD and advanced PVD diffusion barriers and liners which enable Cu plating.
In view of the foregoing problems, drawbacks, and disadvantages of the conventional methods, it is an object of the present invention to provide a structure and method for producing a dual damascene structure.
Another object is to fill small contacts with a highly reliable material and fill wider metal lines with, for example, copper.
In a first aspect of the present invention, a method of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a relatively wider second structure in the dielectric formed on the semiconductor substrate, forming a liner in the first and second structures such that the first structure is substantially filled and the second structure is substantially unfilled, and forming a metallization over the liner to completely fill the second structure.
In a second aspect, a method of forming an interconnect on a semiconductor substrate, includes forming a contact, including a slot, in a dielectric formed on a semiconductor substrate, forming troughs in the dielectric, thereby to form a dual damascene structure (it is noted that the order in which these levels are masked and etched may be reversed), depositing a thick conducting material on the dielectric, depositing a metal over the conducting material to completely fill the slot and metal troughs, removing the metal either to the conducting material or both the metal and the conducting material simultaneously back to the dielectric, and selectively removing the conducting material.
In a third aspect, a semiconductor device, includes a semiconductor substrate, a dual damascene structure formed in at least one dielectric film formed on the semiconductor substrate, including a relatively narrow first structure and a relatively wider second structure, a liner formed in the first and second structures such that the first structure is substantially filled and the second structure is substantially unfilled, and a metallization formed over the liner to completely fill the second structure.
With the unique and unobvious advantages of the present invention, small contacts (e.g., C1 contacts) can be filled with a highly reliable material and wider metal lines (e.g., C1 slots) with, for example, copper.
Further, the invention provides a method for easily and adequately lining contacts for copper filling at contact dimensions below 280 nm, and to lining contacts reliably below contact opening sizes of less than 320 nm.
Moreover, the invention provides a method which is advantageous from a manufacturing perspective in which the number of types of conducting materials that must be implemented in a BEOL process is minimized. Also, the same method can be used to make the DRAM BEOL and the logic BEOL. Thus, a same manufacturing line can produce either DRAM or logic devices with the same type and number of tools.